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Chapter 3: Design Rules and Procedures
3–17
Timing Semantics Between Simulink and HDL Simulation
Startup & Initial Conditions
The testbench includes a global reset for each clock domain. All blocks (except the HDL
Import and MegaCore function blocks) automatically connect any reset on the
hardware to the global asynchronous reset for the clock domain.
When a block explicitly declares an asynchronous reset, this reset is OR ed with the
global reset.
A Global Reset block ( SCLR) , which corresponds to this hardware signal is in the
Altera DSP Builder Blockset IO & Bus library.
The global reset signal is reset before meaningful simulation. When converting from
the Simulink domain to the hardware domain, the reset period is before the Simulink
simulation begins. Therefore, in Simulink simulation, the Global Reset block outputs
only a constant zero and has no simulation behavior. Connect the hardware to reset,
and thus reset at the start of a ModelSim testbench simulation.
1
DSP blocks or MegaCore functions may have additional initial conditions or startup
states that are not automatically reset by the global reset signal.
Initial Reset of HDL Import Blocks and MegaCore Functions in Simulink
Simulations
The ModelSim testbenches have an initial reset cycle, which ModelSim performs,
before simulation. The first 200 cycles are reset, then the testbench puts the test vectors
through. The reset sets the intial state of registers, which may otherwise have 'X'
(unknown) outputs. In Simulink simulations, there is no explicit reset signal—the
Simulink simulation models for DSP Builder blocks assume there is a reset. HDL
import blocks and MegaCore functions do not provide explicit models, but use a
generic HDL simulator. Simulink does not have a way to represent 'X' in its numeric
types— it writes an unknown 'X' as a 0. The HDL import block or MegaCore function
may have registers that require a reset to avoid unknown outputs. Unknown states
may be initially propagating through your imported HDL import block or MegaCore
function. For some imported HDL import blocks or MegaCore functions, these initial
unknown outputs may result in outputs that are different to the ModelSim simulation
(which is reset).
Altera recommends that you must first explicitly reset HDL import blocks and
MegaCore functions in Simulink simulation. If you have any such registers with
unknown outputs in a feedback loop, the Simulink simulation always gives 'X' (zero
in Simulink's numeric types) until reset and the unknown states continue to
propagate.
1
If a block in one clock domain drives a block in another clock domain with an
asynchronous clear port, Simulink may not model the system. An asynchronous clear
only takes full effect if you assert it at the end of a sample; if it is asserted then cleared,
DSP Builder ignores it.
DSP Builder Global Reset Circuitry
By default, Simulink does not graphically display the clock enable and reset input
pins on DSP Builder registered blocks. When DSP Builder converts a design to HDL, it
automatically connects the implied clock enable and reset pins.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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